1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly to a delay circuit formed thereon.
2. Description of the Prior Art
Semiconductor devices often use circuit delay function which may be provided by gate circuits such as inverters to generate various timings on a circuit. In most circuits for obtaining large delay values, gate circuits such as inverters are connected in series in a plurality of stages (cascade connection) so as to obtain the delay value resulting from the sum of the delay values of all the stages of the gate circuits.
In such a case, the number of the circuit stages to be connected in series can be decreased by providing a larger delay value per stage of the gate circuit. An example of the prior art for providing a larger gate delay value per stage has been disclosed, for instance, in Japanese Unexamined Patent Publication No. 61-98011. In this patent publication, a delay circuit has been proposed in which a plurality of p-channel MOS transistors and n-channel MOS transistors are connected in series in a CMOS gate array LSI. The configurations of the conventional delay circuits are shown in FIGS. 1A and 1B.
FIG. 1A shows a circuit configuration in which two stages are connected in series between the power supply and the ground; more specifically, p-channel MOS transistors P1 and P2 and n-channel MOS transistors N1 and N2 are connected in series. The source of the p-channel MOS transistor P1 is connected to a power supply VDD, while the drain thereof is connected to the source of the p-channel MOS transistor P2, the drain of which is connected to the drain of the n-channel MOS transistor N2. The source of the n-channel MOS transistor N2 is connected to the drain of the n-channel MOS transistor N1, the source of which is connected to ground GND. The gate terminals of the transistors N1, N2, P1, and P2 are commonly connected to a signal input terminal IN, and the junction point of the drain of the p-channel MOS transistorP2 and the drain of the n-channel MOS transistor N2 is connected to a signal output terminal OUT.
The delay circuit thus configured operates as an inverter. It is known that the signal delay value of such delay circuit provides a larger delay value than that provided by the delay circuit of the CMOS inverter composed of one p-channel MOS transistor and one n-channel MOS transistor.
FIG. 1B shows another delay circuit configured by connecting three p-channel MOS transistors P1, P2 and P3, and three n-channel MOS transistors N1, N2 and N3 in series between the power supply and the ground.
In this case, the delay value changes as the number of the MOS transistors connected in series is increased as shown in FIG. 2. In FIG. 2, the axis of abscissa indicates the numbers of each group of p-channel MOS transistors and n-channel MOS transistors connected in series, while the axis of ordinate indicates resulting delay value td.
In case of such a type of delay circuit, however, it is known that the delay changes greatly with the number of stages connected in series when an attempt is made to adjust the delay by changing the number of transistors to be connected in series in order to set a desired delay value, thus making it difficult to accomplish fine adjustment of delay value.
For instance, if the number of stages of the p-channel and n-channel MOS transistors to be connected in series is changed from two each as shown in FIG. 1A to three each as shown in FIG. 1B, the delay value will be almost doubled as shown in FIG. 2. This increase in delay corresponds to a change of approximately a several 100 nS in a typical CMOS circuit.
Therefore, in case it is desired to delicately control the delay so as to generate a delay with an accuracy level of, for example, about a several 10 nS, it is necessary to provide other means for adjusting the load capacity other than the delay circuit.
In general, the required configuration calls for wiring, additional gates, etc., resulting in a problem in that an additional space for installing the additional components is required, which means an increase of the space of a chip.